1. Field of the Invention
The present invention relates to the method for manufacturing a bonded SOI wafer using an ion implantation delamination method, and particularly relates to a method for manufacturing the bonded SOI wafer by bonding a silicon single crystal wafer into which hydrogen ions and so forth have been implanted with a base wafer serving as a support substrate and thereafter delaminating it.
2. Description of the Related Art
Recently, as the manufacturing method for the bonded SOI wafer, a method for manufacturing the bonded SOI wafer by bonding an ion-implanted bond wafer and thereafter delaminating it (the ion implantation delamination method: a technology which is also called Smart Cut method (a registered trademark)) has started newly gaining attention.
This ion implantation delamination method is a technology that an oxide film is formed on at least one of two wafers and gas ions such as hydrogen ions, rare gas ions and so forth are implanted into an upper surface of one wafer (a bond wafer) to form an ion-implanted layer (a micro bubble layer) within the wafer, thereafter its surface into which the ions have been implanted is brought into close contact with the other wafer (a base wafer) via the oxide film (an insulator film), thereafter one wafer (the bond wafer) is delaminated so as to remain in the form of a thin film by applying a heat treatment (a delamination heat treatment) or mechanical external force using the ion-implanted layer as a cleavage plane, and a heat treatment (a bonding heat treatment) is further applied to firmly bond them to fabricate the bonded SOI wafer having a thin film (an SOI layer) on the base wafer (see Patent Literature 1). In this method, the bonded SOI wafer which is high in film thickness uniformity of the thin film, in particular, the SOI layer is easily obtained.
However, in a case where the bonded SOI wafer is fabricated by the ion implantation delamination method, a layer damaged by ion implantation exists on a front surface of the bonded SOI wafer in which the delamination has been performed and the surface roughness is increased as compared with a mirror surface of a silicon wafer of the general product level. Therefore, in the ion implantation delamination method, it becomes necessary to eliminate such damaged layer and surface roughness.
Conventionally, in a final process after a bonding heat treatment, mirror polishing (a stock removal: about 100 nm) which is called touch polishing and which is extremely reduced in stock removal has been performed in order to eliminate this damaged layer and so forth.
However, when polishing including machining factors has been performed on the SOI layer, such a problem occurs that the film thickness uniformity of the SOI layer which has been attained to some extent by implantation of hydrogen ions and so forth and delamination is deteriorated because the stock removal of polishing is not uniform.
As a method for solving such a problem, a flattening treatment in which a high-temperature heat treatment is performed in place of the touch polishing to improve the surface roughness comes to be practiced.
For example, in Patent Literature 2, it is proposed to apply a heat treatment under a hydrogen-containing reducing atmosphere (a rapid heating-rapid cooling heat treatment (RTA: Rapid Thermal Annealing)) without polishing the front surface of the SOI layer after the delamination heat treatment (or after the bonding heat treatment). In addition, in Patent Literature 3, it is proposed to form an oxide film on the SOI film by a heat treatment under an oxidizing atmosphere after the delamination heat treatment (or after the bonding heat treatment) and then remove the oxide film (a so-called sacrificial oxidation treatment) and apply the heat treatment under the reducing atmosphere (the rapid heating-rapid cooling heat treatment (the RTA treatment)).
In addition, in Patent Literature 4, flattening of a delaminating plane and avoidance of OSF generation are simultaneously attained by performing the sacrificial oxidation treatment on the SOI wafer in which the delamination has been performed after a flattening heat treatment under an atmosphere of inert gas, hydrogen gas, or mixed gas thereof.
Since the flattening treatment that the high-temperature heat treatment is performed in place of the touch polishing so as to improve the surface roughness has come to be performed as mentioned above, presently, the SOI wafers whose diameter is 300 mm and whose film thickness uniformity that a film thickness range (a value that an in-plane minimum film thickness value has been subtracted from an in-plane maximum film thickness value) of the SOI layer is within 3 nm are being obtained by the ion implantation delamination method in mass production level.
In addition, in Patent Literature 5, the content that co-implantation of ion species of at least two different atoms is performed and “RTA+StabOx (stabilized oxidation)” is performed one or a plurality of time(s) as a finishing step thereof in order to reduce the surface roughness of the delaminating plane is described (see paragraph [0046]). The content that this StabOx (the stabilized oxidation) is performed in the condition of 900° C. oxidation+1100° C. Ar annealing (two hours) is described in paragraph [0078].
Also in paragraph [0087] in Patent Literature 6, the content that “RTA+StabOx+RTA+film thinning” is performed for improvement in surface roughness of the delaminating plane caused by co-implantation of the ion species is described.
Further, although in paragraphs [0035] to [0037] in Patent Literature 7, the RTA and the sacrificial oxidation (Sox) are described as the finishing step in order to reduce defects (critical holes) in the SOI layer, only 1100 C.° is disclosed as the temperature of the SOx (the reference literature of RTA-Sox-RTA-SOx (French Patent) described in paragraph [0039] corresponds to Patent Literature 5).
Further, in Patent Literature 8, a process of delamination→ozone cleaning→hydrogen RTA (1100 to 1250° C.)→sacrificial oxidation→Ar annealing is described in order to reduce concave defects in the SOI layer (in an example, RTA (1150° C./30 sec)+Ar annealing (1200° C./1 hr)).    Patent Literature 1: Japanese Unexamined Patent Application Publication No. H5-211128    Patent Literature 2: Japanese Unexamined Patent Application Publication No. H11-307472    Patent Literature 3: Japanese Unexamined Patent Application Publication No. 2000-124092    Patent Literature 4: WO 2003/009386    Patent Literature 5: Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2007-500435    Patent Literature 6: Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2008-513989    Patent Literature 7: Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2008-526010    Patent Literature 8: Japanese Unexamined Patent Application Publication No. 2009-32972